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digitalmars.D - std.cpuid ARM Issue

reply 9il <ilyayaroshenko gmail.com> writes:
First please see, for example, this ARM CPU

L1 cache per 1 core.
L2 cache per 2 cores.
L3 cache for all (8) cores.

It is critical for multithread BLAS (and D BLAS is going to be 
the best BLAS ever) to estimate that L2 cache is per 2 cores.

In the same time it is impossible to collect information about 
each ARM CPU configuration. Any hope to receive this information 
at runtime?

Best regards,
May 16 2016
parent safety0ff <safety0ff.dev gmail.com> writes:
I don't know ARM specifics, but perhaps hwloc is useful to you: 
May 16 2016