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digitalmars.D.learn - AES-NI

reply "Heinz" <thor587 gmail.com> writes:
Hi,
Are AES-NI instruction set supported by the D inline assembler?
If not, can they be used by inserting raw data (the corresponding
opcodes)? Does anyone know the opcodes for the instruction set?
Thanks
Dec 08 2012
next sibling parent reply =?UTF-8?B?QWxleCBSw7hubmUgUGV0ZXJzZW4=?= <alex lycus.org> writes:
On 08-12-2012 18:08, Heinz wrote:
 Hi,
 Are AES-NI instruction set supported by the D inline assembler?
 If not, can they be used by inserting raw data (the corresponding
 opcodes)? Does anyone know the opcodes for the instruction set?
 Thanks

Yes, they are supported. And yes, you can insert raw machine code with the db, dw, dd, and dq directives. The opcodes can be found in the Intel manual. -- Alex Rønne Petersen alex lycus.org http://lycus.org
Dec 08 2012
parent =?UTF-8?B?QWxleCBSw7hubmUgUGV0ZXJzZW4=?= <alex lycus.org> writes:
On 08-12-2012 21:14, Heinz wrote:
 On Saturday, 8 December 2012 at 17:11:37 UTC, Alex Rønne Petersen wrote:
 On 08-12-2012 18:08, Heinz wrote:
 Hi,
 Are AES-NI instruction set supported by the D inline assembler?
 If not, can they be used by inserting raw data (the corresponding
 opcodes)? Does anyone know the opcodes for the instruction set?
 Thanks

Yes, they are supported. And yes, you can insert raw machine code with the db, dw, dd, and dq directives. The opcodes can be found in the Intel manual.

Thanks for your answer. By supported you mean i can use the mnemonic (AESENC, AESDEC, etc) inside an ASM statement or must i insert the raw machine code with db, dw, etc?

You can use the mnemonics.
 Just in case i've been looking for the corresponding machine codes and
 can not find them, i've searched even in Intel's AES whitepaper with no
 luck.

-- Alex Rønne Petersen alex lycus.org http://lycus.org
Dec 08 2012
prev sibling next sibling parent "Heinz" <thor587 gmail.com> writes:
On Saturday, 8 December 2012 at 17:11:37 UTC, Alex Rønne Petersen 
wrote:
 On 08-12-2012 18:08, Heinz wrote:
 Hi,
 Are AES-NI instruction set supported by the D inline assembler?
 If not, can they be used by inserting raw data (the 
 corresponding
 opcodes)? Does anyone know the opcodes for the instruction set?
 Thanks

Yes, they are supported. And yes, you can insert raw machine code with the db, dw, dd, and dq directives. The opcodes can be found in the Intel manual.

Thanks for your answer. By supported you mean i can use the mnemonic (AESENC, AESDEC, etc) inside an ASM statement or must i insert the raw machine code with db, dw, etc? Just in case i've been looking for the corresponding machine codes and can not find them, i've searched even in Intel's AES whitepaper with no luck.
Dec 08 2012
prev sibling parent "David Nadlinger" <see klickverbot.at> writes:
On Saturday, 8 December 2012 at 20:14:09 UTC, Heinz wrote:
 Just in case i've been looking for the corresponding machine 
 codes and can not find them, i've searched even in Intel's AES 
 whitepaper with no luck.

You probably want to have a look at the Intel Instruction Set Reference document. When I am looking for things like this, I'm tend to be lazy and just search my PDF copy of the »Combined Volume Set of Intel® 64 and IA-32 Architectures Software Developer’s Manuals«, downloadable here: http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html (the documentation for AESENC, for example, is at Vol. 2A, 3-44) David
Dec 08 2012