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reply Manfred Nowak <svv1999 hotmail.com> writes:
http://www.tyan.com/products/html/thunderk8qw.html
is raising the amd design to its limits.

I am still blushing under the thought to develop something in D for 
such hardware. We are at the cusp of public available massive 
parallel machines.

Who feels prepared for such?

-manfred
Nov 16 2005
parent Sean Kelly <sean f4.ca> writes:
Manfred Nowak wrote:
 http://www.tyan.com/products/html/thunderk8qw.html
 is raising the amd design to its limits.
 
 I am still blushing under the thought to develop something in D for 
 such hardware. We are at the cusp of public available massive 
 parallel machines.
 
 Who feels prepared for such?

Have you seen Horus? The price tag might be a bit steep for home machines, but I'm very excited about the possibilities: http://www.hypertransport.org/docs/tech/horus_external_white_paper_final.pdf http://www.realworldtech.com/includes/templates/articles.cfm?ArticleID=RWT120104202353&mode=print Based on in-house performance comparisons between a single Opteron and a Sparc NUMA machine (the Opteron is orders of magnitude faster than the Sparc when operating on medium to large datasets), I'm very excited about SMP Opterons for concurrent programming. I'm also quite interested to see lock-free performance comparisons between a fully loaded Horus machine and a Sparc, given the glaring differences in the memory model between these two platforms. In the long term however, I have a feeling systems will be converging on the Release Consistency model (similar to the Itanium) as it seems a good compromise between simplicity and speed. By comparison, the x86 implements Processor Consistency and in practice is actually Sequentially Consistent in most cases. This being the case, I'm surprised the Opteron scales as well as it does. It's a real testament to the memory controller architecture in this design. Go AMD :-) Sean
Nov 16 2005