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digitalmars.D.announce - new cpuid is ready for comments

reply Ilya Yaroshenko <ilyayaroshenko gmail.com> writes:
Hello :-)

`cpuid` package is core.cpuid analog.
It would be used by future D BLAS implementation.

Why it is better?
See
https://github.com/libmir/cpuid#api-features
https://github.com/libmir/cpuid#implementation-features
https://issues.dlang.org/show_bug.cgi?id=16028

Please report your CPU (GitHub/Gist):

```
dub fetch cpuid
dub test cpuid
```
... AMD was not tested at all and I hope to see your reports.

ARM contributors are wanted!

Destroy!

Best regards,
Ilya


Docs: http://docs.cpuid.dlang.io
GitHub: https://github.com/libmir/cpuid
Dub: cpuid
Jul 11 2016
next sibling parent Guillaume Chatelet <chatelet.guillaume gmail.com> writes:
On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko wrote:
 Hello :-)

 `cpuid` package is core.cpuid analog.
 It would be used by future D BLAS implementation.

 Why it is better?
 See
 https://github.com/libmir/cpuid#api-features
 https://github.com/libmir/cpuid#implementation-features
 https://issues.dlang.org/show_bug.cgi?id=16028

 Please report your CPU (GitHub/Gist):

 ```
 dub fetch cpuid
 dub test cpuid
 ```
 ... AMD was not tested at all and I hope to see your reports.

 ARM contributors are wanted!

 Destroy!

 Best regards,
 Ilya


 Docs: http://docs.cpuid.dlang.io
 GitHub: https://github.com/libmir/cpuid
 Dub: cpuid
Looks good! Here are my results (I added a `cat /proc/cpuinfo` for the record) https://gist.github.com/gchatelet/31a8cf41ba1d888c1efaef314d6a0c97
Jul 12 2016
prev sibling next sibling parent reply Guillaume Chatelet <chatelet.guillaume gmail.com> writes:
On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko wrote:
 Hello :-)

 `cpuid` package is core.cpuid analog.
 It would be used by future D BLAS implementation.
Hey Ilya, Quick question: where do the data come from/how reliable do you think they are?
Jul 12 2016
parent reply Ilya Yaroshenko <ilyayaroshenko gmail.com> writes:
On Tuesday, 12 July 2016 at 12:46:26 UTC, Guillaume Chatelet 
wrote:
 On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko wrote:
 Hello :-)

 `cpuid` package is core.cpuid analog.
 It would be used by future D BLAS implementation.
Hey Ilya, Quick question: where do the data come from/how reliable do you think they are?
Hello Guillaume, The data come from CPUID x86/x86_64 instruction. I have fixed bugs for AMD yesterday. Information for Intel and AMD processors should be reliable. But I am not sure about Cache and TLB information for virtual machines and other vendors. You can use cpuid.x86_any._cpuid [1] to get any information that is not presented. [1] http://docs.cpuid.dlang.io/latest/cpuid_x86_any.html#._cpuid
Jul 12 2016
parent reply Guillaume Chatelet <chatelet.guillaume gmail.com> writes:
On Tuesday, 12 July 2016 at 13:23:46 UTC, Ilya Yaroshenko wrote:
 On Tuesday, 12 July 2016 at 12:46:26 UTC, Guillaume Chatelet 
 wrote:
 On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko wrote:
 Hello :-)

 `cpuid` package is core.cpuid analog.
 It would be used by future D BLAS implementation.
Hey Ilya, Quick question: where do the data come from/how reliable do you think they are?
Hello Guillaume, The data come from CPUID x86/x86_64 instruction. I have fixed bugs for AMD yesterday. Information for Intel and AMD processors should be reliable. But I am not sure about Cache and TLB information for virtual machines and other vendors. You can use cpuid.x86_any._cpuid [1] to get any information that is not presented. [1] http://docs.cpuid.dlang.io/latest/cpuid_x86_any.html#._cpuid
Thx Ilya, I was discussing this a few colleagues. I'm quoting one of them here with his permission: "It doesn't seems that a userland library like this has any possibility to solve the root problem on Android/ARM. It's a twofold problem: 1. On ARM, the registers containing CPU identification and cache structure information, are privileged. See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344f/Chdebced.html etc... (more such registers listed in the left pane on that page) Thus it is up to the operating system to expose this information to userspace. That takes us to the second part of the problem: 2. As far as I know, Android does not expose either CPU identification or cache structure information to userspace. Please do correct me if I'm wrong and this library found a way around that --- but from a cursory look at the cpuid library code, it does not have an ARM implementation at the moment?"
Jul 12 2016
next sibling parent Ola Fosheim =?UTF-8?B?R3LDuHN0YWQ=?= writes:
On Tuesday, 12 July 2016 at 15:24:29 UTC, Guillaume Chatelet 
wrote:
 2. As far as I know, Android does not expose either CPU 
 identification or cache structure information to userspace.

 Please do correct me if I'm wrong and this library found a way 
 around that --- but from a cursory look at the cpuid library 
 code, it does not have an ARM implementation at the moment?"
According to docs: https://developer.android.com/ndk/guides/cpu-features.html Or, probably not recommended or supported: https://github.com/jooink/ndk-cpuid/blob/master/CPUIdApp/jni/com_jooink_experiments_android_ndk_cpuid_CPUIdApp.c
Jul 12 2016
prev sibling next sibling parent Ilya Yaroshenko <ilyayaroshenko gmail.com> writes:
On Tuesday, 12 July 2016 at 15:24:29 UTC, Guillaume Chatelet 
wrote:
 On Tuesday, 12 July 2016 at 13:23:46 UTC, Ilya Yaroshenko wrote:
 On Tuesday, 12 July 2016 at 12:46:26 UTC, Guillaume Chatelet 
 wrote:
 On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko 
 wrote:
 Hello :-)

 `cpuid` package is core.cpuid analog.
 It would be used by future D BLAS implementation.
Hey Ilya, Quick question: where do the data come from/how reliable do you think they are?
Hello Guillaume, The data come from CPUID x86/x86_64 instruction. I have fixed bugs for AMD yesterday. Information for Intel and AMD processors should be reliable. But I am not sure about Cache and TLB information for virtual machines and other vendors. You can use cpuid.x86_any._cpuid [1] to get any information that is not presented. [1] http://docs.cpuid.dlang.io/latest/cpuid_x86_any.html#._cpuid
Thx Ilya, I was discussing this a few colleagues. I'm quoting one of them here with his permission: "It doesn't seems that a userland library like this has any possibility to solve the root problem on Android/ARM. It's a twofold problem: 1. On ARM, the registers containing CPU identification and cache structure information, are privileged. See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344f/Chdebced.html etc... (more such registers listed in the left pane on that page) Thus it is up to the operating system to expose this information to userspace. That takes us to the second part of the problem: 2. As far as I know, Android does not expose either CPU identification or cache structure information to userspace. Please do correct me if I'm wrong and this library found a way around that --- but from a cursory look at the cpuid library code, it does not have an ARM implementation at the moment?"
Thank you for the information, I have not know that registers are privileged on ARM! By "other vendors" I mean other x86 vendors listed in enum VendorIndex [1]. ARM is not supported, but API supports complex topology. So ARM direction is to receive approximate information from an OS, like from /proc/cpuinfo on Linux. Just CPU brand name with version is significant information for cache size. [1] http://docs.cpuid.dlang.io/latest/cpuid_x86_any.html#.VendorIndex
Jul 12 2016
prev sibling parent Kai Nacke <kai redstar.de> writes:
On Tuesday, 12 July 2016 at 15:24:29 UTC, Guillaume Chatelet 
wrote:
 On Tuesday, 12 July 2016 at 13:23:46 UTC, Ilya Yaroshenko wrote:
 On Tuesday, 12 July 2016 at 12:46:26 UTC, Guillaume Chatelet 
 wrote:
 On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko 
 wrote:
 Hello :-)

 `cpuid` package is core.cpuid analog.
 It would be used by future D BLAS implementation.
Hey Ilya, Quick question: where do the data come from/how reliable do you think they are?
Hello Guillaume, The data come from CPUID x86/x86_64 instruction. I have fixed bugs for AMD yesterday. Information for Intel and AMD processors should be reliable. But I am not sure about Cache and TLB information for virtual machines and other vendors. You can use cpuid.x86_any._cpuid [1] to get any information that is not presented. [1] http://docs.cpuid.dlang.io/latest/cpuid_x86_any.html#._cpuid
Thx Ilya, I was discussing this a few colleagues. I'm quoting one of them here with his permission: "It doesn't seems that a userland library like this has any possibility to solve the root problem on Android/ARM. It's a twofold problem: 1. On ARM, the registers containing CPU identification and cache structure information, are privileged. See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344f/Chdebced.html etc... (more such registers listed in the left pane on that page) Thus it is up to the operating system to expose this information to userspace. That takes us to the second part of the problem: 2. As far as I know, Android does not expose either CPU identification or cache structure information to userspace. Please do correct me if I'm wrong and this library found a way around that --- but from a cursory look at the cpuid library code, it does not have an ARM implementation at the moment?"
On Linux/ARM, Linux/PPC, etc. you have to use getauxval(): https://github.com/dlang/druntime/blob/master/src/core/sys/linux/sys/auxv.d See https://lwn.net/Articles/519085/ for background information. Regards, Kai
Jul 15 2016
prev sibling next sibling parent Andrea Agosti <cifvts gmail.com> writes:
On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko wrote:
 Hello :-)

 `cpuid` package is core.cpuid analog.
 It would be used by future D BLAS implementation.

 Why it is better?
 See
 https://github.com/libmir/cpuid#api-features
 https://github.com/libmir/cpuid#implementation-features
 https://issues.dlang.org/show_bug.cgi?id=16028

 Please report your CPU (GitHub/Gist):

 ```
 dub fetch cpuid
 dub test cpuid
 ```
 ... AMD was not tested at all and I hope to see your reports.

 ARM contributors are wanted!

 Destroy!

 Best regards,
 Ilya


 Docs: http://docs.cpuid.dlang.io
 GitHub: https://github.com/libmir/cpuid
 Dub: cpuid
My report, Intel i5 6600K https://gist.github.com/cifvts/213a1e2ab564274b16a2294312cbd6f4
Jul 12 2016
prev sibling next sibling parent Dechcaudron <no-reply no-email.com> writes:
On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko wrote:
 Please report your CPU (GitHub/Gist)
Running on Mac Pro Intel Xeon Quad-Core x2 https://gist.github.com/Dechcaudron/e6eeb17972316785d7c07c409a2ed092
Jul 13 2016
prev sibling next sibling parent drug <drug2004 bk.ru> writes:
Intel(R) Xeon(R) CPU X5690   3.47GHz
https://gist.github.com/drug007/738f7ce8ba73f4413d11e170ab36c7e3

output for cpuid for VM (VirtualBox) running on Intel(R) Xeon(R) CPU 
X5690   3.47GHz
https://gist.github.com/drug007/76750ba962e84be494b8bf11bd84a3a7

output cpuid for Intel(R) Core(TM) i7-3770 CPU   3.40GHz
https://gist.github.com/drug007/3f7f0701b3d4f1f40c422acc36e343d7
Jul 14 2016
prev sibling next sibling parent reply Brad Jones <brad emailaddress.org> writes:
On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko wrote:
 Hello :-)

 `cpuid` package is core.cpuid analog.
 It would be used by future D BLAS implementation.

 Why it is better?
 See
 https://github.com/libmir/cpuid#api-features
 https://github.com/libmir/cpuid#implementation-features
 https://issues.dlang.org/show_bug.cgi?id=16028

 Please report your CPU (GitHub/Gist):

 ```
 dub fetch cpuid
 dub test cpuid
 ```
 ... AMD was not tested at all and I hope to see your reports.

 ARM contributors are wanted!

 Destroy!

 Best regards,
 Ilya


 Docs: http://docs.cpuid.dlang.io
 GitHub: https://github.com/libmir/cpuid
 Dub: cpuid
Very nicely done. Following Guillaume, I too have added the output of `cat /proc/cpuinfo`. Here's my contribution. cpuid for Intel(R) Core(TM) i5-6260U CPU 1.80GHz on Intel NUC: https://gist.github.com/britishempire/dad6f7d0e24dff096d7ef35e62520387
Jul 14 2016
parent Brad Jones <bjon085 aucklanduni.ac.nz> writes:
On Thursday, 14 July 2016 at 12:00:12 UTC, Brad Jones wrote:

 Very nicely done. Following Guillaume, I too have added the 
 output of `cat /proc/cpuinfo`. Here's my contribution.

 cpuid for Intel(R) Core(TM) i5-6260U CPU   1.80GHz on Intel NUC:
 https://gist.github.com/britishempire/dad6f7d0e24dff096d7ef35e62520387
In the off chance a 404 is thrown: https://gist.github.com/brdjns/dad6f7d0e24dff096d7ef35e62520387
Jul 14 2016
prev sibling next sibling parent reply Kirill Babikhin <mrakobes86reg yandex.ru> writes:
On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko wrote:
 Please report your CPU (GitHub/Gist):
AMD Phenom(tm) 9550 Quad-Core Processor https://gist.github.com/qsimpleq/78ed456a289f9cc418f69527298e3e9a
Jul 14 2016
parent Kirill Babikhin <mrakobes86reg yandex.ru> writes:
On Thursday, 14 July 2016 at 13:04:56 UTC, Kirill Babikhin wrote:

Intel(R) Core(TM)2 CPU 4400   2.00GHz
https://gist.github.com/qsimpleq/78ed456a289f9cc418f69527298e3e9a#file-intel-r-core-tm-2-cpu-4400-2-00ghz
Jul 14 2016
prev sibling next sibling parent Marco Leise <Marco.Leise gmx.de> writes:
Am Mon, 11 Jul 2016 16:30:44 +0000
schrieb Ilya Yaroshenko <ilyayaroshenko gmail.com>:

 Please report your CPU (GitHub/Gist):
Instead of yet another Haswell/Broadwell, here is an oldie but goldie: A 16 year old Pentium-III-M from an IBM T23 notebook: https://gist.github.com/mleise/4ed5637371ca5cea07bef8241adc7d80 I repost this in your bug tracker momentarily. -- Marco
Jul 14 2016
prev sibling next sibling parent Jack Stouffer <jack jackstouffer.com> writes:
On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko wrote:
 Please report your CPU (GitHub/Gist):
Late 2015 MacBook Pro Intel i5 https://gist.github.com/JackStouffer/6870bde82788ae039afe0aaf0d7bf4ba
Jul 14 2016
prev sibling next sibling parent Claude <no no.no> writes:
Intel Core i5:
https://gist.github.com/claudemr/aa99d03360dccc65d7967651011dc8ca
Jul 15 2016
prev sibling next sibling parent burjui <bytefu gmail.com> writes:
AMD FX 8350
test     
https://gist.github.com/burjui/a661499a2daa93302395d136b6c99152
cpuinfo  
https://gist.github.com/burjui/8c10924284c1c1f9cce33bcd2b71d863
Jul 15 2016
prev sibling next sibling parent reply Claude <no no.no> writes:
On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko wrote:
 ARM contributors are wanted!
What exactly do you need for ARM architecture? I have an ARM target and I have tried to run a library[1] to get some CPU info. I hacked in the source files to just build and link the CPU info code. I used an arm-gcc toolchain (I don't know how to cross-compile using ldc... yet). And it's built on a native Linux OS. And it seems to work. Here's the output I have after running the code: https://gist.github.com/claudemr/98b5a4bb83e8d967b31a3044e4d81c0f Most of it is C code. There is some ARM assembly code, some of which is inlined, and some is in a ".S" file to test specific instructions. Is it what you're looking for? [1] It's called "Yeppp", and looks like what you want to do with MIR: http://www.yeppp.info/ Have you come across it?
Jul 15 2016
parent reply Ilya Yaroshenko <ilyayaroshenko gmail.com> writes:
On Friday, 15 July 2016 at 12:10:22 UTC, Claude wrote:
 On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko wrote:
 [...]
What exactly do you need for ARM architecture? I have an ARM target and I have tried to run a library[1] to get some CPU info. I hacked in the source files to just build and link the CPU info code. I used an arm-gcc toolchain (I don't know how to cross-compile using ldc... yet). And it's built on a native Linux OS. And it seems to work. Here's the output I have after running the code: https://gist.github.com/claudemr/98b5a4bb83e8d967b31a3044e4d81c0f Most of it is C code. There is some ARM assembly code, some of which is inlined, and some is in a ".S" file to test specific instructions. Is it what you're looking for?
Yes! Finally we need the final code for LDC, it support ARM assembler. http://wiki.dlang.org/LDC_inline_assembly_expressions
 [1] It's called "Yeppp", and looks like what you want to do 
 with MIR: http://www.yeppp.info/
 Have you come across it?
No, I have not. Thank you for the link!
Jul 15 2016
parent Claude <no no.no> writes:
On Friday, 15 July 2016 at 15:05:53 UTC, Ilya Yaroshenko wrote:
 On Friday, 15 July 2016 at 12:10:22 UTC, Claude wrote:
 [...]
Yes! Finally we need the final code for LDC, it support ARM assembler. http://wiki.dlang.org/LDC_inline_assembly_expressions
 [...]
No, I have not. Thank you for the link!
I uploaded the code I used from Yeppp there: https://github.com/claudemr/cputest It's a bit of the mess as it is, but it works, and it looks like there is a thorough test of what features ARM hardware may provide.
Jul 15 2016
prev sibling next sibling parent jmh530 <john.michael.hall gmail.com> writes:
On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko wrote:
 Please report your CPU (GitHub/Gist):
Intel(R) Core(TM) i7 CPU 950 3.07GHz https://gist.github.com/jmh530/2f1694711085176e007461ae8218a759 Intel(R) Core(TM) i3-4130T CPU 2.90GHz https://gist.github.com/jmh530/90c8737e7526b8abf4183a8b16a66448 Intel(R) Core(TM) i5-5675C CPU 3.10GHz https://gist.github.com/jmh530/183fa2e86fd0118af10a99ca297f6f79 Intel(R) Core(TM) i3-2100 CPU 3.10GHz https://gist.github.com/jmh530/8265e31cce291126159ae7fb988bacb0 I also have an Intel Xeon E5-2660 2.2GHz running a FreeNAS server, but it would kind of be a pain to figure out how to run DMD in a jail. Oh, and I have a Intel Pentium Dual Core G2030 currently just sitting in a box.
Jul 15 2016
prev sibling next sibling parent "H. S. Teoh via Digitalmars-d-announce" writes:
On Mon, Jul 11, 2016 at 04:30:44PM +0000, Ilya Yaroshenko via
Digitalmars-d-announce wrote:
[...]
 Please report your CPU (GitHub/Gist):
 
 ```
 dub fetch cpuid
 dub test cpuid
 ```
 ... AMD was not tested at all and I hope to see your reports.
[...] AMD Phenom(tm) II X6 1055T Processor (hexacore): https://gist.github.com/quickfur/801c2ee6549194d7a9ccbd024ab60aaa T -- Once the bikeshed is up for painting, the rainbow won't suffice. -- Andrei Alexandrescu
Jul 15 2016
prev sibling next sibling parent Kai Nacke <kai redstar.de> writes:
Output cpuid for Intel(R) Core(TM) i5-3320M CPU   2.6 GHz:
https://gist.github.com/redstar/a1c9c85f17f2c24834050b5b0b734d3d
Jul 15 2016
prev sibling next sibling parent Zoadian <no no.no> writes:
On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko wrote:
 Please report your CPU (GitHub/Gist):
my results for Intel Core i7-6700K CPU 4.00GHz rev.2 (the one with sgx) https://gist.github.com/Zoadian/f53d818e714a849ba7f34bbec2f3339a awesome!
Jul 15 2016
prev sibling parent Guillaume Chatelet <chatelet.guillaume gmail.com> writes:
On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko wrote:
 Hello :-)

 `cpuid` package is core.cpuid analog.
 It would be used by future D BLAS implementation.

 Why it is better?
 See
 https://github.com/libmir/cpuid#api-features
 https://github.com/libmir/cpuid#implementation-features
 https://issues.dlang.org/show_bug.cgi?id=16028

 Please report your CPU (GitHub/Gist):

 ```
 dub fetch cpuid
 dub test cpuid
 ```
 ... AMD was not tested at all and I hope to see your reports.

 ARM contributors are wanted!

 Destroy!

 Best regards,
 Ilya


 Docs: http://docs.cpuid.dlang.io
 GitHub: https://github.com/libmir/cpuid
 Dub: cpuid
Also: Intel(R) Atom(TM) CPU 230 1.60GHz https://gist.github.com/gchatelet/d3d347e4630ec2567eae7fe0391a9316
Jul 19 2016