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digitalmars.D.announce - SSE128

reply Manfred Nowak <svv1999 hotmail.com> writes:
AMD announces one further step in SIMD:

http://developer.amd.com/articles.jsp?id=171&num=1

-manfred
Jun 08 2007
parent reply Bill Baxter <dnewsgroup billbaxter.com> writes:
Manfred Nowak wrote:
 AMD announces one further step in SIMD:
 
 http://developer.amd.com/articles.jsp?id=171&num=1
 
 -manfred

From what I can tell it's vectorized 128-bit ops, allowing, say, 4 floats to be added to another 4 floats in one op. Didn't we have that already in SSE3? Is this just AMD's version of SSE3? Anyone know what's different? --bb
Jun 08 2007
parent Sean Kelly <sean f4.ca> writes:
Bill Baxter wrote:
 Manfred Nowak wrote:
 AMD announces one further step in SIMD:

 http://developer.amd.com/articles.jsp?id=171&num=1

 -manfred

From what I can tell it's vectorized 128-bit ops, allowing, say, 4 floats to be added to another 4 floats in one op. Didn't we have that already in SSE3? Is this just AMD's version of SSE3? Anyone know what's different?

It also supports operations on 128-bit floating point values, though I don't know if that's mentioned in the linked article. Sean
Jun 08 2007