digitalmars.D - Intel's new AVX instruction set
- Don <nospam nospam.com.au> Jun 18 2008
I haven't seen this mentioned before on the newsgroup, but I think this is very significant for thinking about the future of D. http://softwareprojects.intel.com/avx/ Essentially they're extending the SSE floating point registers to 256 bits (8 float operations at once instead of 4; 4 doubles instead of 2). And the instruction set has future expansion to 1024 bits for floating point (32 floats at once!), while integer operations can potentially reach 512 bits. Additionally, floating point multiply-and-accumulate is included. The previous proposed instruction sets (Intel's SSE4 and AMD's SSE5) didn't look terribly useful. But this one looks excellent. Note that it is announced for 2010, and there's no guarantee that it will happen. Even if it does, it's unlikely to be mainstream for at least 5 years. But it's worth thinking ahead. Probably the main consequence for D is that memory alignment (of float and double arrays) is going to be critical. Some of the new instructions require alignment to a 32-byte boundary.
Jun 18 2008