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D - Impulse Memory Controller

reply Mark Evans <Mark_member pathlink.com> writes:
Since D aspires to be a systems language, more attention
should be paid to novel architectures, especially those
targeting D's favorite topic, runtime performance.
This group is working on novel memory controllers and
associated compiler tools.

http://www.cs.utah.edu/impulse/

"Von Neumann's prediction of 1945 continues to hold true -
memory is the primary system bottleneck."
Jun 19 2003
parent "Sean L. Palmer" <palmer.sean verizon.net> writes:
Hell yeah!

It would be great even at present time if the compiler was smart enough to
know where to insert prefetch instructions.  Before the start of a loop,
prefetch the first data, and at the start of a loop, prefetch the *next*
iteration's data (should be easily predictable in most loops).  This can't
be much harder than unrolling and scheduling.

Any situation where the compiler knows ahead of time what data is going to
need accessed later, and such data isn't likely to already be in the cache,
is an appropriate situation to do prefetching.  Prefetching may not help,
but it rarely hurts (usually when you prefetch stuff that's already in the
L1 cache, well, it's a wasted CPU cycle) and has potential to drastically
improve execution time.

Sean

"Mark Evans" <Mark_member pathlink.com> wrote in message
news:bctf6r$vlg$1 digitaldaemon.com...
 Since D aspires to be a systems language, more attention
 should be paid to novel architectures, especially those
 targeting D's favorite topic, runtime performance.
 This group is working on novel memory controllers and
 associated compiler tools.

 http://www.cs.utah.edu/impulse/

 "Von Neumann's prediction of 1945 continues to hold true -
 memory is the primary system bottleneck."

Jun 20 2003